Serial NOR FLASH/MRAM is a type of non-volatile memory (similar to EEPROM) which is typically used for storing programs to be executed by processors. The memories are also used to store transitional data or for logging events in high speed telecommunication products. The memories include a serial peripheral interface (SPI). An SPI controller interfaces the memory with the processor.
The SPI NOR flash memories are available from a size of few Mbits up to 2 Gigabits currently. There are currently NOR flash memories from multiple vendors (e.g. Micron, Winbond, Macronix, Spansion) available in the market. Though the general functional behavior of all these flash memories is similar there are minor implementation and operational differences across them. MRAM on the other hand is currently believed to be available from a single vendor (Everspin). The current available size of MRAM is 1 Mbits, although the size of MRAM is expected to go higher in the future.
Serial NOR flash/MRAM memories typically support a Quad SPI interface consisting of one clock pin, a chip select pin and four data pins. The clock and chip select pins are always driven by SPI controller. The Quad SPI interface may be operated in traditional Standard SPI mode, Extended SPI mode, Dual mode as well as Quad mode. In all these modes, clock and chip select pins are used in same fashion. The data lane usage in each mode is different. In Standard SPI mode, two data lanes are operated in uni-directional mode, one as input and the other one as output. In Dual mode, two data lanes are operated in bi-directional mode. In Quad mode, four data lanes are operated in bi-directional mode. In extended mode, part of the SPI transfer happens in standard mode while remaining operations are performed with data lanes similar to dual/quad mode.
Typically, to perform any operation on FLASH/MRAM (read, write, etc.) the SPI controller provides a clock signal and instructions on one or more data lanes (up to a maximum of four data lanes) after asserting the memory chip select. The instructions comprise of an OPCODE (a number corresponding to a particular operation such as read/write), followed by relevant information to complete the operation. The memory interprets the first 8 bits of data received after chip select assertion as the OPCODE of a new instruction. For example, in case of a fast read operation, the first 8 bit OPCODE is followed by memory address for which the operation is to be performed against, followed by dummy clock cycles, and followed by memory posting the read data. The number of dummy clock cycles required varies based on the fast read mode and the memory vendor. FIG. 1 shows an example timing diagram 100 illustrating how an SPI controller generates clock (SCLK), chip select (CS#) and data signals (SIO0, SIO1, SIO2, SIO3). In the illustrated example the SPI controller performs a Quad output fast read (OPCODE=0x6B) on an example NOR flash memory. In this mode the OPCODE and address are provided on single lane (SIO0) while data is read on four lanes.
FLASH/MRAM memory devices support many read modes, mostly differentiated by the number of data lanes used for transferring OPCODE, ADDRESS and DATA. Table 1 lists the various read modes supported by SPI flash/MRAM memory devices.
TABLE 1# Data # Data # DataLines Lines ModeLines forforforRead ModeIdentifierOPCODEAddressDataREADOPCODE =1110x03FAST READOPCODE =1110x0BDUAL OUTPUT FASTOPCODE =112READ (DOFR)0x3BDUAL INPUT/OUTPUTOPCODE =122FAST READ (DIOFR)0xBBQUAD OUTPUT FASTOPCODE =114READ (QOFR)0x6BQUAD INPUT/OUTPUTOPCODE =144FAST READ (QIOFR)0xEBFull Dual (DIO)Identified by222Full Quad (QIO)memory444internalconfigurationExecute in Place (XIP)Device-No Depends on the specificOPCODEOPCODE usedsequenceswhile entering required toXIP. (e.g., 4 enter/exit XIPaddress, 4 data (XIP enterfor OPCODEsequences0xEB)include anOPCODE toselect readmode).
The initial modes in which the OPCODE is sent on the single data lane, the mode itself is identified based on the OPCODE value. For full Quad/Dual modes where OPCODE is also sent on 4/2 lanes, the SPI controller needs to pre-configure the Flash/MRAM device. There are minor variations across various memory devices on how to pre-configure the device for these operating modes.
The XIP mode is a special read mode supported by memory vendors, to maximize read performance. The XIP mode is only a mode for reading and none of the currently available FLASH/MRAM memory devices support a similar mode (without OPCODE) for performing writes. In XIP mode, the memory does not require an OPCODE and is only provided with a read address. The memory interprets all transactions on the SPI interface as read transactions without OPCODE till XIP mode is exited. The number of bit lanes used for transferring address and data in XIP mode depends on the read OPCODE used while entering XIP mode as noted in Table 1 above.
Table 2 shows the benefit of using XIP mode based on the throughput and latency observed in verification for various read modes in different read scenarios.
TABLE 2Continuoussequential read32 byte random4 byte randomReadthroughputread throughputread throughputRead latencymodeMbps% QOFRMbps% QOFRMbps% QOFRns% QOFRQOFR384.16100202.6410047.11100630100QIOFR384.98100.21237.23117.0664.66137.2541065.07QIO385.17100.26252.84124.7773.82156.6935055.55XIP (in385.41100.32259.35127.9978.46166.5433052.38QIOFR)
Though all current memory device vendors support such a mode, the name of the mode can change across vendors; some call it XIP (execute in place) others call this mode as “Performance enhance mode” or “Continuous read mode”. There are also implementation differences between devices from different vendors. For example, devices from different vendors use different signal values sent during dummy cycles to enter and exit XIP mode, as discussed further below.
FIG. 2 shows an example timing diagram 200 illustrating how XIP mode is entered in an example Macronix flash memory with 0xEB (QIOFR mode). In the illustrated example, a read OPCODE 202 (EAh/EBh) is provided on one data line (SIO0) followed by address 204 followed by a pattern 206 (dummy cycle value) which puts the memory device into XIP mode. The read OPCODE 202 determines the number of data lines to be used in XIP mode. The example XIP entry sequence of FIG. 2 includes the OPCODE (EAh/EBh) for QIOFR mode, so all four data lines are used for addresses and data. Once in XIP mode data is read out 218 on all four data lines. A subsequent address 214 is provided on all four data lines, and after a configurable number of dummy cycles 216, data is again read out 218. Repeated reads may be performed without any intervening OPCODEs while in the XIP mode.
XIP mode is the highest throughput, lowest latency read mode supported by SPI NOR flash/MRAM memories, in which the memory does not require a read OPCODE on chip select assertion. The flash/MRAM implementation on how to enter and exit XIP varies across memory vendors. Not all memory vendors support enabling XIP mode by default using non-volatile configuration registers. So in general, on a boot interface, a SPI controller starts reading in basic modes where most memory devices behave in similar fashion. Based on the initial boot code the SPI controller moves to XIP mode for enhanced performance. The challenges in following the boot scheme include handling a chip warm reset where only the SPI controller gets reset while the SPI memory device does not get power cycled. The SPI controller on receiving the reset goes back to basic read mode while the SPI memory device remains in XIP mode, causing re-boot failures.
The inventors have determined a need for improved methods and apparatus for controlling SPI memory devices.